IEEE CICC 2024

A 7.4μW and 860μm² per channel cryo-CMOS IC for 70-channel frequency-multiplexed μs-readout of semiconductor qubits

Abstract

Large-scale quantum computing holds promise for exponentially faster computation speed to address currently unsolvable problems. Nevertheless, biasing, driving and reading numerous physical qubits operating at cryogenic temperature remains an on-going challenge. In particular, the integration of cryogenic control and readout ICs appears mandatory to overcome the wiring bottleneck [1, 2, 3]. In this regard, the promising higher operating temperature (up to 1K) of silicon semiconductor qubits offers a more substantial cryogenic power budget, which could enable addressing larger qubit arrays with integrated cryogenic CMOS electronics. In the context of 100,000 qubits at 1K, the maximum power consumption allowed by cooling capability is about 1W within a compact footprint of just a few cm², defining targets of <10μW/qubit consumption and <0.01mm²/qubit footprint. Focusing on the readout IC, the semiconductor-qubit coherence time also imposes a typical <100μs readout time, while requiring a Bit Error Rate (BER) below 10-3.

Publication : Le Monde

Author(s)

Tristan Meunier

CTO & co-founder

All authors

Quentin Schmidt , Brian Martinez , Thomas Houriez , Baptiste Jadot , Aloysius Jansen , Xavier Jehl , Tristan Meunier , Gaël Pillonnet , Gérard Billiot , Adrien Morel , Yvain Thonnart , Franck Badets