To run useful quantum algorithms in a fault-tolerant manner, several ingredients will be necessary, not least of which are robust quantum gates that are not too sensitive to environmental changes and control electronics that are suitable for large-scale systems.
A closer look at quantum gates
The Loss-di Vincenzo qubit, one of the most prominent spin qubits being used in semiconductor quantum circuits, relies on a single charge trapped in a quantum dot. The underlying semiconductor band structure plays a key role in defining the qubit’s spin properties and the quantum system’s energy spectrum.
Because this qubit is a “spin-1/2” object (which means, in its most basic sense, that the qubit needs two full rotations, or 720°, to arrive back in its original position), the application of a magnetic field creates a canonical two-level system. This is the way we define the individual qubit.
Once this magnetic field is applied, the energy of the qubit as compared with the system’s other energy levels (valley, orbital excited energy, etc.) is quite different. This means that leakage outside of the qubit space is negligible during the manipulation of the qubit.
For quantum gates to be truly functional, the minimum requirements for silicon spin qubits are:
- The existence of quantum dot arrays
- A means of controlling the dot potential and tunneling between dots
- Charge detection to probe the qubits
- Excitation antennae to enable radiofrequency magnetic manipulation of the spin
These are the “tools” used to engineer the three main quantum gates—measurement, one-qubit, and two-qubit—that form the universal set of gates. These gates are underpinned by two fundamental principles:
- Radiofrequency-driven quantum systems, which leverage techniques borrowed from nanomagnetic resonance (NMR) to write quantum information on qubits using one-qubit gates.
- The Pauli exclusion principle, which enables the strong spin-spin interaction needed for quantum entanglement and two-qubit gates.
Semiconductor spin qubits offer the added functionality of displacing qubits in a controlled manner. This is where the coherent displacement gate comes in. It makes transferring qubits between distant quantum cores possible, which could open the door to new manipulation schemes and scaling opportunities.
At Quobly, we are currently working with research partners to measure the quality of the different gate implementation methods with the goal of refining our plan for large-scale architectures.
Singularity of decoherence in spin qubits
Like with any qubit, in silicon spin qubits, decoherence is the enemy of high-fidelity quantum gates. In this kind of qubit, the choice has been made to encode quantum information in the spin degree of freedom of the charge carriers. This is because spin is largely separated from the charge properties and, therefore, protected from the strong electrical disturbances present in semiconductor devices. In addition, by using Silicon 28, a nuclear-free silicon isotope, a quasinoiseless environment well-suited to preserving the fragile quantum information manipulated during a quantum calculation can be created. And, due to the microscopic nature of the qubit, this solid-state environment also enables exceptional coherence times. Coherence time is ultimately limited by spin relaxation time, or the time it takes for the particle’s spin to decay.
The spin relaxation time has been proven to take up to several tenths of seconds for individually-isolated spin qubits. This exceptionally “long” coherence time is closely related to the relative protection of the spin degree of freedom from electrical disturbances.
Decoherence is characterized by significant asymmetry between bit flips and phase flips. Bit flips are related to the aforementioned spin relaxation processes. As stated, they have been proven to take up to several seconds. Phase flip coherence times have only been measured up to a few ms. This asymmetry is intimately related to the different processes induced by the semiconductor environment.
At Quobly, we are investigating the factors that limit spin qubit coherence from a technological point of view, and the consequences of the spin qubit noise properties on fault-tolerant quantum computing in order to optimize the complete architecture of our quantum processor.
The cryocontrol unit
The spin qubit research and development community has now demonstrated the ability to fulfill all the basic gate requirements for quantum computing. The focus has now shifted to increasing the number of qubits and engineering spin-based quantum processors at the intermediate and large scales.
Whether it is for spin qubits or for other quantum computing technologies, the question of scalability is also one that must be answered. The level of control that can be achieved and maintained at this scale is a major challenge.
The ability to engineer a control unit and a quantum system on the same chip and qubit tolerance to operating temperatures where strong cooling capabilities are available (above 100 mW) are two of semiconductor spin qubits’ main differentiators. In addition, the ability to tightly integrate classical transistors and qubits reduces control and readout overhead and keeps the size of a qubit with all quantum functionalities to a minimum.
At Quobly, we are exploring ways to engineer the qubit unit with all the functionalities while keeping overall chip size down.
Bringing it all together
As stated earlier, silicon spin qubits present a unique opportunity to engineer the quantum system and the control unit on the same chip. They also offer potential tolerance for higher operating temperatures—a major differentiator considered an enabler for large-scale quantum computing and error correction implementation. While the final system architecture still needs further investigation, Quobly has devised an initial plan to scale to a 100-logical-qubit quantum processor unit.
For the time being, we are measuring the performance of the individual modules to refine their specifications. Our overall focus remains on the quantum unit itself and the potential of existing VLSI processes in Tier 1 foundries for scaling up semiconductor quantum circuits.
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